What is ARM Cortex-M architecture? Simple explanation with diagram

By Know.it editorial teamPublished 17 September 2026Updated 11 November 20267 min readEnglish

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Quick answer

ARM Cortex-M is a family of small processor cores designed by ARM. The core holds the ALU, registers, a three-stage pipeline, the NVIC interrupt controller, a SysTick timer and a debug unit. It talks to Flash, SRAM and peripherals through ICode, DCode and System buses joined by a bus matrix.

In one lineARM Cortex-M is a family of compact 32-bit processor core designs that ARM licenses to chip makers, who wrap each core with memory, timers and pins to build a complete microcontroller.

Think of your school tiffin box. The box is the chip. Inside sits a small steel container that holds the actual food — that container is the processor core. ARM Cortex-M is that inner container: a design, not the whole box.

Here's the fun part. ARM doesn't sell you chips. It sells the design and the rules. Companies like ST, NXP and TI take that design, add Flash memory, RAM, timers and pins, and give you a ready chip. So the same Cortex-M core shows up in many different chips, each with its own extras. Let's build the whole picture, box by box.

What is ARM Cortex-M? Core design vs full chip

ARM Cortex-M is a family of small processor cores — the 'brain' — designed by ARM. ARM only makes the design and the instruction rules. It doesn't manufacture the chip you hold in your hand.

The chip makers do that job. ST, NXP and TI take the Cortex-M core and build a complete microcontroller around it, adding Flash, RAM, timers and GPIO pins. That's why one Cortex-M core can appear in chips from different companies, with different memory sizes and different peripherals.

ARM: core design plus instruction rules
ST, NXP, TI: the full chip — memory, timers, pins
Same core, different chips — the extras change, the core stays

A quick everyday comparison

Think of a car. One engine design can sit inside many car models. The engine maker doesn't build the whole car — the car company adds the body, seats and wheels. Cortex-M is that engine design, and the chip maker builds the rest of the vehicle around it.

What blocks are inside the Cortex-M core?

Open the core box and you'll find a handful of blocks, each with one clear job. The processor core does the maths and holds the registers. The NVIC (Nested Vectored Interrupt Controller) handles urgent events. SysTick is a small timer built right into the core.

Bus interfaces are the roads that connect the core to memory and devices. And the debug unit lets you pause the chip and look inside — set a breakpoint, step one instruction at a time, read the registers. That's the block that helps you hunt down bugs.

Processor core: ALU for arithmetic plus registers
NVIC: picks and prioritises interrupts
SysTick: built-in timer for regular ticks
Bus interfaces: paths to memory and devices
Debug unit: breakpoints, single-stepping, register reads

Registers explained: R0–R12, SP, LR and PC

Registers are a tiny notepad inside the core, with named slots. R0 to R12 are the general-purpose ones — they hold the numbers you're working on right now. Fast, small, and always right next to the ALU.

Then come three special ones. SP, the stack pointer, says where the next item goes on the stack. LR, the link register, remembers where to return when a function finishes. PC, the program counter, points at the next instruction. Miss these three and nothing makes sense.

Common mistake to avoid

Don't treat SP, LR and PC like ordinary notepads. If you overwrite the stack pointer carelessly, the core loses track of where its saved data lives. If you clobber the link register, a function won't know where to go back. Treat them with respect.

How does the three-stage pipeline work?

Picture a roti line. One person rolls the dough, another cooks it, a third packs it. All three work at the same time on different rotis. That's a pipeline.

In Cortex-M the three stages are fetch, decode and execute. Fetch brings the next instruction from memory. Decode works out what it means. Execute actually does the job. Because the stages overlap, one instruction finishes in every clock cycle — even though each single instruction still passes through all three stages.

Fetch: bring the next instruction from memory
Decode: figure out what it's asking
Execute: carry out the work
Overlap means one instruction completes per cycle

Memory map and buses: how the core reaches Flash, SRAM and peripherals

Code lives in Flash. Working data lives in SRAM. Peripherals like GPIO and timers are memory-mapped, which simply means they also appear as addresses — the core talks to them the same way it talks to memory.

The core uses three roads. The ICode bus carries instructions. The DCode bus carries data. The System bus handles slower peripherals. A bus matrix joins all of these, so traffic can flow without everything waiting in one queue.

ICode bus: instructions from Flash
DCode bus: data to and from SRAM
System bus: peripheral reads and writes
Bus matrix: the junction connecting them all

What happens when you press a button? Interrupts step by step

Let's follow one button press all the way through. You press the button. The GPIO peripheral raises an interrupt. The NVIC picks the highest-priority interrupt and looks up the handler's address in the interrupt vector table.

Before jumping, the core saves its context — PC, LR and the registers it needs — onto the stack. Then it jumps to the handler and runs it. When the handler returns, the saved context is loaded back, and the main program carries on exactly where it left off.

Button pressed
GPIO peripheral raises an interrupt
NVIC applies priority and reads the vector table
Core saves context on the stack
Handler runs
Context restored, main program resumes

Build the architecture diagram step by step

Now let's draw it ourselves. Start with one box in the middle: processor core plus registers. That's your anchor.

Next, add the NVIC and SysTick inside that core box. Then add the debug unit, also inside. Now draw the bus matrix outside the core. Finally, connect Flash, SRAM and peripherals to the bus matrix. Label every arrow with what travels on it — instructions on ICode, data on DCode, peripheral reads and writes on the System bus.

Step 1: core box with processor core and registers
Step 2: add NVIC and SysTick inside the core
Step 3: add the debug unit inside the core
Step 4: draw the bus matrix outside the core
Step 5: connect Flash, SRAM and peripherals to the matrix
Step 6: label each arrow with what it carries

Key takeaways

Cortex-M is a core design family, not a single chip.
ARM designs the core; ST, NXP and TI build the full chip around it.
Registers R0–R12 are the working notepad; SP, LR and PC are the special ones.
The three-stage pipeline (fetch, decode, execute) overlaps work so one instruction finishes per cycle.
The NVIC handles urgent interrupts and the SysTick timer keeps regular time.
ICode, DCode and System buses, joined by a bus matrix, connect the core to Flash, SRAM and peripherals.

Key terms

Core: The processor 'brain' inside a chip that executes instructions.
Register: A tiny, fast storage slot inside the core holding current values.
NVIC: Nested Vectored Interrupt Controller — prioritises and dispatches interrupts.
SysTick: A small timer built into the core for regular time ticks.
Pipeline: Overlapping instruction stages so work finishes faster.
Memory-mapped I/O: Peripherals that appear as memory addresses to the core.
Bus matrix: The junction connecting the core's buses to memory and peripherals.
Interrupt vector table: A table holding the addresses of interrupt handler functions.

Practice questions

Which block decides which interrupt runs first?
- (a) SysTick
- (b) The ALU
- (c) The NVIC
- (d) The debug unit
Answer key
(c) The NVIC — The NVIC compares priorities and picks the highest-priority interrupt.
What does the PC register hold?
- (a) The address of the next instruction
- (b) The last computed result
- (c) The stack location
- (d) The interrupt priority
Answer key
(a) The address of the next instruction — PC, the program counter, points at the next instruction to fetch.
In the pipeline, what happens in the decode stage?
- (a) The instruction is fetched from Flash
- (b) The core works out what the instruction means
- (c) The result is written to SRAM
- (d) The handler address is looked up
Answer key
(b) The core works out what the instruction means — Decode translates the fetched instruction into something the core can execute.
Which bus carries data to and from SRAM?
- (a) ICode bus
- (b) System bus
- (c) Debug bus
- (d) DCode bus
Answer key
(d) DCode bus — The DCode bus handles data access, while ICode fetches instructions.
What does the core do before jumping to an interrupt handler?
- (a) It resets the whole chip
- (b) It saves its context on the stack
- (c) It turns off the SysTick timer
- (d) It clears all registers to zero
Answer key
(b) It saves its context on the stack — Saving PC, LR and needed registers lets the program resume exactly where it stopped.

Frequently asked questions

Is ARM Cortex-M a chip?

No. Cortex-M is a family of processor core designs. ARM licenses the design to chip makers like ST, NXP and TI, who add Flash, RAM, timers and pins to build a complete microcontroller. So you'll find the same Cortex-M core inside many different chips.

What does the NVIC do?

The NVIC is the interrupt controller inside the core. When a peripheral raises an interrupt, the NVIC decides which one has the highest priority and finds the handler's address in the interrupt vector table. It makes sure urgent events get handled quickly and in the right order.

Why is the pipeline only three stages?

A short pipeline keeps the design small and predictable, which suits microcontrollers. With fetch, decode and execute overlapping, one instruction finishes every clock cycle. Simpler hardware also means lower power use — handy for battery-run devices.

What is the difference between the ICode and DCode buses?

The ICode bus fetches instructions, usually from Flash. The DCode bus carries data, usually to and from SRAM. Keeping them separate means instruction fetches and data access don't block each other, so the core keeps moving.

What is the debug unit for?

The debug unit lets you pause the chip and look inside. You can set breakpoints, run one instruction at a time, and read the registers. It's the block that turns a mysterious crash into something you can actually trace and fix.

Quick recap: Cortex-M is a small core design that ARM licenses, and chip makers wrap it with memory, timers and pins. Inside sit the processor core and registers, the NVIC, SysTick and the debug unit, all feeding out through ICode, DCode and System buses joined by a bus matrix. Draw those boxes once and the whole architecture sticks.

Sources and further reading

Watch the animated lesson: What is ARM Cortex-M architecture? Simple explanation with diagram (Know.it)
ARM architecture family — en.wikipedia.org
Microcontroller — en.wikipedia.org
Instruction pipelining — en.wikipedia.org
Interrupt — en.wikipedia.org

Know.it editorial team

Written by the Know.it editorial team from the script of an animated Know.it lesson, checked against the lesson's own facts and the sources listed below. Know.it turns any question into a short visual lesson with voice and animation.

Reviewed: 11 November 2026 · Editorial standards · AI transparency

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